# tutorial 2 (modules and decoders)

Completed the 2nd tutorial from the same YouTube channel in Verilog. There is a link to the video below.  I am starting to like translating from VHDL to Verilog; it’s a nice little puzzle sometimes.  I think that I’m just going to post all of my code because I know how frustrating it can be when people describe the things they’ve done but don’t show you how to do it.

There are three modules here: the first decodes an integer value to display on a seven-segment display, the second splits a large number into its individual digits, and the third is the main module that creates the counter and uses instances of the other modules.  Add all of these files to the project and use the main module as the top-level entity.

https://github.com/christopherhays/my-modules

Here is the YouTube tutorial I am working from:

``` // seven-segment decoder
// takes an input 0-15 and returns the values to drive the display

module sev_seg_decoder(in_value, out_value);

input [3:0] in_value;
output [6:0] out_value;
reg [6:0] result;

always@(in_value) begin
case (in_value)
0: result = 7'b1000000;
1: result = 7'b1111001;
2: result = 7'b0100100;
3: result = 7'b0110000;
4: result = 7'b0011001;
5: result = 7'b0010010;
6: result = 7'b0000010;
7: result = 7'b1111000;
8: result = 7'b0000000;
9: result = 7'b0010000;
10: result = 7'b0001000;
11: result = 7'b0000011;
12: result = 7'b1000110;
13: result = 7'b0100001;
14: result = 7'b0000110;
15: result = 7'b0001110;
endcase
end

assign out_value = result;

endmodule

```
``` // digit splitter
// splits an input signal into 4 output signals
// value -> thousands hundreds tens ones

module digit_splitter(in_value, out0, out1, out2, out3);

input [13:0] in_value;   // about 16k max, needed to be over 10k

output [3:0] out0, out1, out2, out3;

reg [13:0] temp;
reg [3:0] t0, t1, t2, t3;

always@(in_value) begin
temp = in_value;
if (temp > 999) begin
t3 = temp/1000;
temp = temp - t3*1000;
end
else
t3 = 0;
if (temp > 99) begin
t2 = temp/100;
temp = temp - t2*100;
end
else
t2 = 0;
if (temp > 9) begin
t1 = temp/10;
temp = temp - t1*10;
end
else
t1 = 0;
t0 = temp;
end

assign out0 = t0;
assign out1 = t1;
assign out2 = t2;
assign out3 = t3;

endmodule

```
``` // Christopher Hays 12/30/16
// demo #2 from the same youtube channel

module sevseg(CLOCK_50, KEY, SW, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7);

input CLOCK_50;
input [3:0] KEY;
input [17:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;

wire [3:0] ones, tens, hundreds, thousands;

reg [25:0] prescaler = 0;     // roughly 64M
reg [13:0] counter = 0;       // roughly 16k

assign HEX4 = 127;      // turn off the highest 4 displays
assign HEX5 = 127;
assign HEX6 = 127;
assign HEX7 = 127;

// instantiate the splitter
digit_splitter S0 (.in_value(counter), .out0(ones), .out1(tens), .out2(hundreds), .out3(thousands));

// instantiate the decoders
sev_seg_decoder D0 (.in_value(ones), .out_value(HEX0));
sev_seg_decoder D1 (.in_value(tens), .out_value(HEX1));
sev_seg_decoder D2 (.in_value(hundreds), .out_value(HEX2));
sev_seg_decoder D3 (.in_value(thousands), .out_value(HEX3));

always@(posedge CLOCK_50) begin
if (prescaler < 100000 * SW)     // augmented by the value on the switches
prescaler = prescaler + 1;
else
prescaler = 0;

if (prescaler == 0) begin
if (KEY == 1) begin
if (counter < 9999)
counter = counter + 1;
else
counter = 0;
end
else begin
if (counter > 0)
counter = counter -1;
else
counter = 9999;
end
end
end      // end always

endmodule

```